1. Field of the Invention:
The invention relates generally to computer systems, and more particularly to a virtual subsystem architecture that simulates isochronous or xe2x80x9creal-time runxe2x80x9d peripheral subsystems transparently to existing software programs.
2. Description of Related Art:
Computer systems generally include provisions for attachment of peripheral subsystems, typically through the use of an add-on card. These subsystems are identified or xe2x80x9cmappedxe2x80x9d through memory and I/O address space recognized by the central processing unit (CPU). In the PC environment, defacto protocols have arisen from the somewhat arbitrary memory and I/O mapping made popular through commercially successful products, such as, but not limited to, sound cards, modems, and graphics display adapters. Application software exists which implicitly embeds these defacto protocolsxe2x80x94making hardware upgrades which deviate from backward compatibility undesirable.
Imposing backward compatibility on peripheral enhancements usually limits performance, increases costs, and requires additional space, typically in the form of additional integrated circuits or die space. The alternative to maintaining backward compatibility is highly unattractive or commercially unacceptable in that a plethora of legacy software must be abandoned.
By way of further background, CPU pipelining techniques are known for mitigating the latency associated with executing complex instructions. More specifically, instruction execution is broken down into multiple xe2x80x9cphasesxe2x80x9d so that more than one instruction in a series of instructions, are executed at any one given time, albeit in different phases.
A related, but not entirely relevant technique to the present invention is the SuperState(trademark) mode of operation described in the Product Briefs for the CHIPSystem(trademark) Architecture, dated Oct. 1991, by Chips and Technologies, Inc., of San Jose, Calif. In this so-called xe2x80x9cSuperState(trademark) modexe2x80x9d, software and hardware incompatibilities are reconciled by intercepting or xe2x80x9ctrappingxe2x80x9d incompatible software commands or interrupts at the external bus level and translating them into a compatible format. This xe2x80x9cSuperStatem(trademark) modexe2x80x9d, which is directed to xe2x80x9cdemand servicexe2x80x9d peripherals, is completely devoid of any teachings or suggestions of eliminating isochronous xe2x80x9creal-time runxe2x80x9d peripherals having critical timing constraints, such as, but not limited to, sound cards and modems. Moreover, the xe2x80x9cSuperState(trademark) modexe2x80x9d is completely devoid of any teachings or suggestions of handling memory mapped I/O in a virtual environment, handling virtual subsystems with a heavily pipelined CPU core, or using hardware resources, such as, but not limited to, counters, timers, comparators, and CODECS, to assist the virtual subsystems and which are remappable among the virtual subsystems to avoid duplication.
From the foregoing, it can be seen that there is a need for a virtual subsystem architecture that handles memory mapped I/O in a virtual environment, handles virtual subsystems with a heavily pipelined CPU core, and provides remappable virtual hardware resources, for virtualizing isochronous real-time run peripheral subsystems.
To overcome the limitations of the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a virtual subsystem architecture employing a native central processing unit along with a reentrant system management mode mechanism with multiple threads of execution, for trapping and servicing events which are intended to provoke a response from a physical subsystem in near real-time. External and internal trap mechanisms generate a System Management Interrupt (SMI) responsive to the occurrence of predetermined external and internal events, respectively. Responsive to the SMI, the native central processing unit determines the event that caused the interrupt and executes a series of instructions to simulate a response expected from the physical subsystem.
A feature of the present invention is the ability to virtualize subsystems with a heavily pipelined CPU core.
Another feature of the present invention is the ability to virtualize memory mapped physical subsystems.
Another feature of the present invention is the ability to virtualize multiple real-time run peripherals through the use of a reentrant system management mode mechanism.
Another feature of the present invention is remappable virtual hardware resources.
Another feature of the present invention is a high degree of integration and amortization of native central processing unit bandwidth to run both application software and to virtualize physical subsystems.
Another feature of the present invention is direct efficiency dependency of the virtualized subsystems on the speed of the native central processing unit.
Another feature of the present invention is that virtualized subsystems are independent of the operating system.
Another feature of the present invention is that virtualized subsystems do not require any special memory management handlers.
Another feature of the present invention is the ease of upgrading new programming for virtualized subsystems.
Another feature of the present invention is a reduction in the manufacturing cost of the computer system.
These and various other objects, features, and advantages of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and forming a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to the accompanying descriptive matter, in which there is illustrated and described a specific example of a virtual subsystem architecture, practiced in accordance with the principles of the present invention.